For more efficient use of grid power, the power factor correction technology has been widely used in the switching power supply technology. In the prior art, it is common practice to insert a power factor correction (PFC) circuit between the diode rectifier bridge and the load of the circuit so that the current drawn from the AC supply is also a sine wave signal and its phase changes with the supply voltage. After inserting the power factor correction circuit, the power factor value can be close to 1.
The implementation of a PFC circuit is shown in FIG. 1, which is applied to a boost converter. The boost converter comprises an inductor L, a switch device S, a freewheeling diode D, an output capacitor Cout and an integrated PFC circuit. The supply voltage Vac serves as an input voltage of the boost converter after passing the diode rectifier bridge, the boost converter converts the input voltage to obtain the output voltage Vout. The PFC circuit comprises an error amplifier U1, a multiplier U2, a comparator U3, an RS flip-flop U4, a driver module U5, and a zero current detection circuit (ZCD) U6. The PFC circuit samples the output voltage Vout and inputs it to the error amplifier U1. One input of the multiplier U2 is the output error feedback signal Verror of the error amplifier U1 and the other input is the divided signal Vin of the supply voltage Vac, so that the output current waveform becomes a sine wave following the supply voltage waveform. A sampling resistor R1 and the external switch device S are connected in series to obtain a switch current signal. When a voltage of the sampling resistor R1 is higher than an output of the multiplier U2, the comparator U3 and the RS flip-flop U4 turn over and turn off the external switch device S by the driver module U5. When the zero current detection circuit U6 detects that the inductor current drops to 0, the external switch device S is turned on. The above control mode realizes the critical conduction mode control through a simple way, which is especially suitable for power factor correction circuit with small and medium power.
From the standpoint of stability, the open-loop gain (Gloop) of the PFC circuit is proportional to the square of the supply voltage Vac, the load (Rload) and the gain (K) of the multiplier, which is:Gloop=Vac2×Rlaod×K  (1)
In the above PFC circuit, the loop gain is equal to the open-loop gain (Gloop). Since the loop gain is a single-pole system, the unity-gain bandwidth increases as the loop gain increases, which may cause instability of the circuit.
In view of the above problem, one solution is to use a non-linear multiplier, that is, to reduce the gain of the multiplier correspondingly when the input voltage increases, thereby approximately maintaining a constant loop gain. However, the solution has disadvantages of sacrificing the performance of the multiplier and increasing the distortion and non-linearity, which may reduce the power factor correction effect of the PFC circuit.
Another solution to this problem is to introduce a voltage feed-forward circuit that compensates for changes in gain by voltage feed-forward. Specifically, to obtain a peak voltage of the input voltage, the peak voltage is input to the multiplier for operation after passing a 1/V2 circuit, so that the loop gain can be made independent of the input voltage. The solution maintains the linearity of the multiplier, so a better power factor correction effect can be obtained.
In the prior art, a voltage feed-forward circuit is implemented as shown in FIG. 2, which uses an external resistor Rff and an external capacitor Cff to form a peak voltage holding circuit. When the input voltage Vin changes rapidly, the internal charge circuit would rapidly charge the external capacitor Cff. When the input voltage Vin is rapidly reduced, the detection module U7 would turn on the switching transistor M2 to quickly discharge charges on the external capacitor Cff to achieve fast follow-up of changes in the input voltage. The disadvantage of the voltage feed-forward circuit in FIG. 2 is that an additional PIN is required to connect the external resistor Rff and the external capacitor Cff. In addition, the values of the external capacitor Cff and the external resistor Rff are compromised, for example, if the external capacitor Cff values too low, there would be a greater ripple on the external capacitor Cff, thereby affecting the output of the multiplier, increasing the distortion, and reducing the power factor correction effect. If the external capacitor Cff values too high, the response is slowed down, which needs longer time to set the correct voltage feed-forward value, thereby causing larger over-voltage or under-voltage in the output voltage.
Therefore, providing a technical proposal to further improve these defects becomes an urgent issue at present.